NRCC
NOTICE OF REGISTRATION CONFIRMATION EMAILED
02/17/2026
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Official data from USPTO
UCIE UNIVERSAL CHIPLET INTERCONNECT EXPRESS
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Active USPTO registrationType: CombinedOffice: United States
Risk and opportunity diagnosis
Executive reading for naming, filing, and monitoring decisions.
USPTO status
Active USPTO registration
Case type
Application and registration
Recorded events
19
Latest update
02/17/2026
Trademark type
Combined
Nice classes
16, 35, 42
Filing date
06/12/2025
Registration date
02/17/2026
Expiration date
-
Complete case details
Structured fields from the responsible authority and the official record.
Status date
02/17/2026
Last transaction
02/17/2026
Responsible office
United States Patent and Trademark Office
Status code
700
Official register
Principal Register
First use anywhere
06/23/2022
First use in commerce
06/23/2022
Drawing code
3
Owner type
54
Owner location
Beaverton, OR
Examiner
SABAGH, LAILA TAREK
Law office
N90
Current location
FILE REPOSITORY (FRANCONIA)
Mark description
The mark consists of two interconnected squares offset at a diagonal. The top square has two smaller squares on the top left and the lower square has a small square on the bottom right, followed by the bolded letters "UCIE" in large font, together forming the first line of the design, followed by the wording "UNIVERSAL" in bold font then "CHIPLET" forming the second line of text, and the third line being formed by the words "INTERCONNECT EXPRESS".
Holders and representatives
Holders
Universal Chiplet Interconnect Express, Inc.
Representatives
Frank X. Curci Buchalter, PC
Technical classification
Nice Classes
Class 16Class 35Class 42
Vienna Codes
No Vienna codes available.
Goods and services
Class 16
Printed materialtechnical documents featuring voluntary technical specifications and standards for interconnects for integrated circuits and other silicon components used for processingmemorystoragecommunicationfor power-efficient and high-speed enhancements to such interconnects
Class 35
Association servicespromoting the design and development of voluntary technical specifications and standards for interconnects for integrated circuits and other silicon components used for processingmemorystoragecommunicationfor power-efficient and high-speed enhancements to such interconnectsfor its members
Class 42
Developing and establishing voluntary technical specifications and standards for interconnects for integrated circuits and other silicon components used for processingmemorystoragecommunicationfor power-efficient and high-speed enhancements to such interconnectstechnical documents for the same
Publications
History of USPTO decisions and trademark events.
19 publications found
R.PR
REGISTERED-PRINCIPAL REGISTER
02/17/2026
NPUB
OFFICIAL GAZETTE PUBLICATION CONFIRMATION E-MAILED
12/30/2025
PUBO
PUBLISHED FOR OPPOSITION
12/30/2025
NONP
NOTIFICATION OF NOTICE OF PUBLICATION E-MAILED
12/24/2025
ERRR
ON HOLD - ELECTRONIC RECORD REVIEW REQUIRED
12/05/2025
CNSA
APPROVED FOR PUB - PRINCIPAL REGISTER
11/25/2025
TEME
TEAS/EMAIL CORRESPONDENCE ENTERED
11/24/2025
CRFA
CORRESPONDENCE RECEIVED IN LAW OFFICE
11/24/2025
TROA
TEAS RESPONSE TO OFFICE ACTION RECEIVED
11/24/2025
GEAN
NOTIFICATION OF EXAMINER'S AMENDMENT/PRIORITY ACTION E-MAILED
11/05/2025
GEAP
EXAMINER'S AMENDMENT/PRIORITY ACTION E-MAILED
11/05/2025
EPEN
COMBINED EXAMINER'S AMENDMENT/PRIORITY ACTION AUTOMATIC ENTRY
11/05/2025
CPEA
EXAMINERS AMENDMENT AND/OR PRIORITY ACTION - COMPLETED
11/05/2025
DOCK
ASSIGNED TO EXAMINER
11/01/2025
MDSC
NOTICE OF DESIGN SEARCH CODE E-MAILED
10/20/2025
NWOS
NEW APPLICATION OFFICE SUPPLIED DATA ENTERED
10/20/2025
MAFR
APPLICATION FILING RECEIPT MAILED
06/12/2025
NWAP
NEW APPLICATION ENTERED
06/12/2025
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