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Official data from USPTO

STATSCHIPPAC

Did you know this trademark is already registered in United States?

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Active USPTO registrationType: CombinedOffice: United States

Quick snapshot

STATSCHIPPAC

ST13

US500000098494542

Class

40, 42

Filing

98494542

Registration

7742781

Risk and opportunity diagnosis

Executive reading for naming, filing, and monitoring decisions.

USPTO status

Active USPTO registration

Case type

Application and registration

Recorded events

24

Latest update

07/23/2026

Trademark type

Combined

Nice classes

40, 42

Filing date

04/11/2024

Registration date

04/01/2025

Expiration date

-

Complete case details

Structured fields from the responsible authority and the official record.

Status date

04/01/2025

Last transaction

07/23/2026

Responsible office

United States Patent and Trademark Office

Status code

700

Official register

Principal Register

Filing basis

Intent to use

First use anywhere

05/06/2024

First use in commerce

05/06/2024

Drawing code

5

Owner type

99

Owner location

Singapore, SG

Examiner

DELANEY, ZHALEH SYBIL

Law office

M70

Current location

FILE REPOSITORY (FRANCONIA)

Mark description

The mark consists of the stylized wording STATSChipPAC.

Holders and representatives

Holders

Stats Chippac Pte. Ltd.

Representatives

Audra Kemp Neal & McDevitt, LLC

Technical classification

Nice Classes

Class 40Class 42

Vienna Codes

No Vienna codes available.

Goods and services

Class 40

Custom assembly and custom manufacture of electrical and electronic componentselectrical semi-conductorssemi-conductor chips or deviceselectrical integrated circuitsintegrated circuit packagingintegrated circuit chips or devices for others; providing technical information in the field of product manufacturing of electrical and electronic componentselectrical semi-conductorssemi-conductor chips or deviceselectrical integrated circuitsintegrated circuit packagingintegrated circuit chips or devicestechnical consulting and manufacturing process consulting related thereto

Class 42

Software engineering services; engineering and testing services in the field of assemblypackagingencasingdesign of electrical and electronic componentselectrical semi-conductorssemi-conductor chips or deviceselectrical integrated circuitsintegrated circuit packaging and integrated circuit chips or devicesfor others; engineering consulting services relating to testingassemblypackaging encasing analysiswafer probewafer sortdesign of electrical and electronic componentselectrical semi-conductorssemi-conductor chips or deviceselectrical integrated circuitsintegrated circuit packaging and integrated circuit chips or devices; providing facilities featuring equipment for others for testing electrical and electronic componentselectrical semi-conductorssemi-conductor chips or devices for quality control purposes and for scientific research purposes; development and establishment of testing specifications and proceduresincluding wafer sorting proceduresall for the purpose of testing of electrical and electronic componentselectrical semi-conductorssemi-conductor chips or deviceselectrical integrated circuitsintegrated circuit packaging and integrated circuit chips or devices; final product quality testing services in the field of electrical and electronic componentselectrical semi-conductorssemi-conductor chips or deviceselectrical integrated circuitsintegrated circuit packaging and integrated circuit chips or devices; packaging design services for others in the field of packaging for electrical and electronic componentselectrical semi-conductorssemi-conductor chips or deviceselectrical integrated circuitsintegrated circuit chips or devices; product research and development services relating to electrical and electronic componentselectrical semi-conductorssemi-conductor chips or deviceselectrical integrated circuitsintegrated circuit packaging and integrated circuit chips or devices; providing scientific and technical information in the field of product designproduct developmentproduct engineeringproduct testing of electrical and electronic componentselectrical semi-conductorssemi-conductor chips or deviceselectrical integrated circuitsintegrated circuit packaging and integrated circuit chips or devicesadvice and consultation relating thereto

Publications

History of USPTO decisions and trademark events.

24 publications found

NRCC

NOTICE OF REGISTRATION CONFIRMATION EMAILED

04/01/2025

R.PR

REGISTERED-PRINCIPAL REGISTER

04/01/2025

NPUB

OFFICIAL GAZETTE PUBLICATION CONFIRMATION E-MAILED

02/11/2025

PUBO

PUBLISHED FOR OPPOSITION

02/11/2025

NONP

NOTIFICATION OF NOTICE OF PUBLICATION E-MAILED

02/05/2025

CNSA

APPROVED FOR PUB - PRINCIPAL REGISTER

01/16/2025

IUAA

USE AMENDMENT ACCEPTED

01/16/2025

XAEC

EXAMINER'S AMENDMENT ENTERED

01/16/2025

GNEN

NOTIFICATION OF EXAMINERS AMENDMENT E-MAILED

01/16/2025

GNEA

EXAMINERS AMENDMENT E-MAILED

01/16/2025

CNEA

EXAMINERS AMENDMENT -WRITTEN

01/16/2025

TEME

TEAS/EMAIL CORRESPONDENCE ENTERED

12/18/2024

CRFA

CORRESPONDENCE RECEIVED IN LAW OFFICE

12/18/2024

TROA

TEAS RESPONSE TO OFFICE ACTION RECEIVED

12/18/2024

ATRV

ATTORNEY REVIEW COMPLETED

11/08/2024

AUPC

AMENDMENT TO USE PROCESSING COMPLETE

10/28/2024

IUAF

USE AMENDMENT FILED

10/28/2024

EAAU

TEAS AMENDMENT OF USE RECEIVED

10/28/2024

GPRN

NOTIFICATION OF PRIORITY ACTION E-MAILED

10/25/2024

GPRA

PRIORITY ACTION E-MAILED

10/25/2024

CPRA

PRIORITY ACTION WRITTEN

10/25/2024

DOCK

ASSIGNED TO EXAMINER

10/24/2024

NWOS

NEW APPLICATION OFFICE SUPPLIED DATA ENTERED

09/23/2024

NWAP

NEW APPLICATION ENTERED

04/11/2024

Continuous trademark protection

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