R.PR
REGISTERED-PRINCIPAL REGISTER
05/09/2023
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Official data from USPTO
CDNA
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Active USPTO registrationType: WordOffice: United States
Risk and opportunity diagnosis
Executive reading for naming, filing, and monitoring decisions.
USPTO status
Active USPTO registration
Case type
Application and registration
Recorded events
32
Latest update
05/09/2023
Trademark type
Word
Nice classes
9
Filing date
09/22/2020
Registration date
05/09/2023
Expiration date
-
Complete case details
Structured fields from the responsible authority and the official record.
Status date
05/09/2023
Last transaction
05/09/2023
Responsible office
United States Patent and Trademark Office
Status code
700
Official register
Principal Register
Filing basis
Intent to use
First use anywhere
08/10/2020
First use in commerce
11/30/2020
Drawing code
4
Owner type
03
Owner location
Santa Clara, CA
Examiner
DELGIZZI, RONALD ERNEST
Law office
L70
Current location
PUBLICATION AND ISSUE SECTION
Holders and representatives
Holders
Advanced Micro Devices, Inc.
Representatives
Belinda J. Scrimenti Wilkinson Barker Knauer, LLP
Technical classification
Nice Classes
Class 9
Vienna Codes
No Vienna codes available.
Goods and services
Class 9
Integrated circuitsgraphics integrated circuits; integrated circuit chip sets; cards containing integrated circuits; integrated circuit chips; semiconductor devices; semiconductor chips; semiconductors; chipsets; computer hardware; microprocessors; microprocessor subsystems comprised of one or more microprocessorscentral processing unit (CPU)CPU coresdownloadable and recorded software for operating the foregoing; computer hardware subsystems comprised of microprocessor subsystems; microprocessor modules; system-on-a-chip (SOC) processors; system-on-a-chip (SoC) architecture for use with central processing units (CPU) and graphics processing units (GPU)system-on-a-chip (SoC) architecture that connects die-to-diechip-to-chipsocket-to-socketused across different microprocessors for enabling increased computing performance; system-on-a-chip (SoC) architecture for use with multiple graphics processing units (GPU)system-on-a-chip (SoC) architecture that connects die-to-diechip-to-chipsocket-to-socketused across multiple different microprocessorsoptimized for machine learning and high-performance computing applicationsto enhance GPU to GPU connectivityto enable increased computing performanceto accelerate data center computer workloadsto enable exascale-class supercomputers; network-on-a-chipmicroprocessor hardware technology for use in scaling for high performance computing (HPC) and machine learning (ML) that provides for computer network interfaces across microprocessor central processor unit (CPU) and graphics processing unit (GPU) corescomputer memoryhubs and data fabric for enabling microprocessor communications and increasing computing performance and efficiency; microprocessor communication fabricdata communication interconnect architecture responsible for collecting datacommand control interconnect architecture responsible for data sensor telemetry; data fabrichardware and downloadable and recorded software that supports storageprocessinganalysis and management of disparate data; graphics processors units (GPUs); graphics processing units (GPU); GPU cores; graphics cards; accelerated data processors; computer accelerator board; graphics accelerators; graphics processor subsystemmicroprocessor subsystems comprised of one or more microprocessorsgraphics processing units (GPUs)GPU coresdownloadable and recorded software for operating the foregoing; supercomputers; computer servers; network servers; computer workstationscomputers designed for advanced technical or scientific applications and high performance computing applications; digital media streaming devices; solid state drives; computer memory devicesvolatile memory devices; dynamic random-access memory (DRAM); dynamic random access memory (DRAM) controllers; downloadable and recorded software for operating all of the foregoing; downloadable and recorded computer software for operating computer and graphics processors
Publications
History of USPTO decisions and trademark events.
32 publications found
NRCC
NOTICE OF REGISTRATION CONFIRMATION EMAILED
05/09/2023
SUNA
NOTICE OF ACCEPTANCE OF STATEMENT OF USE E-MAILED
04/01/2023
CNPR
ALLOWED PRINCIPAL REGISTER - SOU ACCEPTED
03/31/2023
EXRA
NOTICE OF APPROVAL OF EXTENSION REQUEST E-MAILED
03/11/2023
SUPC
STATEMENT OF USE PROCESSING COMPLETE
03/10/2023
EX2G
SOU EXTENSION 2 GRANTED
03/10/2023
AITU
CASE ASSIGNED TO INTENT TO USE PARALEGAL
03/10/2023
IUAF
USE AMENDMENT FILED
02/27/2023
EXT2
SOU EXTENSION 2 FILED
02/27/2023
EEXT
SOU TEAS EXTENSION RECEIVED
02/27/2023
EISU
TEAS STATEMENT OF USE RECEIVED
02/27/2023
EXRA
NOTICE OF APPROVAL OF EXTENSION REQUEST E-MAILED
08/31/2022
EX1G
SOU EXTENSION 1 GRANTED
08/29/2022
EXT1
SOU EXTENSION 1 FILED
08/29/2022
EEXT
SOU TEAS EXTENSION RECEIVED
08/29/2022
NOAM
NOA E-MAILED - SOU REQUIRED FROM APPLICANT
03/01/2022
ETOP
EXTENSION OF TIME TO OPPOSE PROCESS - TERMINATED
01/16/2022
ETOF
EXTENSION OF TIME TO OPPOSE RECEIVED
10/07/2021
NPUB
OFFICIAL GAZETTE PUBLICATION CONFIRMATION E-MAILED
09/07/2021
PUBO
PUBLISHED FOR OPPOSITION
09/07/2021
NONP
NOTIFICATION OF NOTICE OF PUBLICATION E-MAILED
08/18/2021
CNSA
APPROVED FOR PUB - PRINCIPAL REGISTER
08/03/2021
TEME
TEAS/EMAIL CORRESPONDENCE ENTERED
07/14/2021
CRFA
CORRESPONDENCE RECEIVED IN LAW OFFICE
07/13/2021
TROA
TEAS RESPONSE TO OFFICE ACTION RECEIVED
07/13/2021
GNRN
NOTIFICATION OF NON-FINAL ACTION E-MAILED
01/13/2021
GNRT
NON-FINAL ACTION E-MAILED
01/13/2021
CNRT
NON-FINAL ACTION WRITTEN
01/13/2021
DOCK
ASSIGNED TO EXAMINER
01/09/2021
NWOS
NEW APPLICATION OFFICE SUPPLIED DATA ENTERED
11/01/2020
NWAP
NEW APPLICATION ENTERED
09/25/2020
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